View ATTINY13V-10MU_1489901.PDF datasheet online --- IC-ON-LINE

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2535gs?avr?01/07 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 120 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips througput at 20 mhz ? non-volatile progra m and data memories ? 1k byte of in-system progra mmable program memory flash endurance: 10,000 write/erase cycles ? 64 bytes in-system programmable eeprom endurance: 100,000 write/erase cycles ? 64 bytes internal sram ? programming lock for self-progra mming flash program and eeprom data security ? peripheral features ? one 8-bit timer/counter with prescaler and two pwm channels ? 4-channel, 10-bit adc with internal voltage reference ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? external and internal interrupt sources ? low power idle, adc noise reduction, and power-down modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit ? internal calibrated oscillator ? i/o and packages ? 8-pin pdip/soic: six programmable i/o lines ? 20-pad mlf: six programmable i/o lines ? operating voltage: ? 1.8 - 5.5v for attiny13v ? 2.7 - 5.5v for attiny13 ? speed grade ? attiny13v: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 10 mhz @ 2.7 - 5.5v ? attiny13: 0 - 10 mhz @ 2.7 - 5.5v, 0 - 20 mhz @ 4.5 - 5.5v ? industrial temp erature range ? low power consumption ? active mode: 1 mhz, 1.8v: 240a ? power-down mode: < 0.1a at 1.8v 8-bit microcontroller with 1k bytes in-system programmable flash attiny13v attiny13 summary rev. 2535gs?avr?01/07
2 attiny13 2535gs?avr?01/07 pin configurations figure 1. pinout attiny13 overview the attiny13 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful in structions in a single clock cycle, the attiny13 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. 1 2 3 4 8 7 6 5 (pcint5/reset/adc0/dw) pb5 (pcint3/clki/adc3) pb3 (pcint4/adc2) pb4 gnd vcc pb2 (sck/adc1/t0/pcint2) pb1 (miso/ain1/oc0b/int0/pcint1) pb0 (mosi/ain0/oc0a/pcint0) pdip/soic 1 2 3 4 5 qfn/mlf 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 (pcint5/reset/adc0/dw) pb5 (pcint3/clki/adc3) pb3 dnc dnc (pcint4/adc2) pb4 dnc dnc gnd dnc dnc vcc pb2 (sck/adc1/t0/pcint2) dnc pb1 (miso/ain1/oc0b/int0/pcint1) pb0 (mosi/ain0/oc0a/pcint0) dnc dnc dnc dnc dnc note: bottom pad should be soldered to ground. dnc: do not connect
3 attiny13 2535gs?avr?01/07 block diagram figure 2. block diagram program counter internal oscilla tor watchdog timer stack pointer program flash sram mcu control register general purpose registers instruction register timer/ counter0 instruction decoder data dir. reg.port b data register port b programming logic timing and control mcu status register status register alu port b drivers pb0-pb5 vcc gnd control lines 8-bit databus z adc / analog comparator interrupt unit calibrated y x reset clki watchdog oscillator data eeprom
4 attiny13 2535gs?avr?01/07 the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the attiny13 provides the following featur es: 1k byte of in-system programmable flash, 64 bytes eeprom, 64 bytes sram, 6 general purpose i/o lines, 32 general pur- pose working registers, one 8-bit timer/c ounter with compare modes, internal and external interrupts, a 4-channel, 10-bit adc, a programmable watchdog timer with internal oscillator, and three software selectable power saving modes. the idle mode stops the cpu while allowing the sram, time r/counter, adc, analog comparator, and interrupt system to continue functioning. the power-down mode saves the register con- tents, disabling all chip functions until the next interrupt or hardware reset. the adc noise reduction mode stops the cpu and all i/o modules except adc, to minimize switching noise during adc conversions. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be re-programmed in-system through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the avr core. the attiny13 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-cir- cuit emulators, and evaluation kits. pin descriptions vcc digital supply voltage. gnd ground. port b (pb5..pb0) port b is a 6-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the attiny13 as listed on page 50. reset reset input. a low level on this pin for longer than the minimu m pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 12 on page 31. shorter pulses are not guaranteed to generate a reset.
5 attiny13 2535gs?avr?01/07 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f sreg i t h s v n z c page 7 0x3e reserved ? ? ? ? ? ? ? ? 0x3d spl sp[7:0] page 9 0x3c reserved ? 0x3b gimsk ? int0 pcie ? ? ? ? ? page 55 0x3a gifr ? intf0 pcif ? ? ? ? ? page 55 0x39 timsk0 ? ? ? ? ocie0b ocie0a toie0 ? page 72 0x38 tifr0 ? ? ? ? ocf0b ocf0a tov0 ? page 73 0x37 spmcsr ? ? ? ctpb rflb pgwrt pgers selfprgen page 99 0x36 ocr0a timer/counter ? output compare register a page 72 0x35 mcucr ?pudsesm1sm0 ? isc01 isc00 page 50 0x34 mcusr ? ? ? ? wdrf borf extrf porf page 34 0x33 tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 page 68 0x32 tcnt0 timer/counter (8-bit) page 72 0x31 osccal oscillator calibration register page 23 0x30 reserved ? 0x2f tccr0a com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 page 71 0x2e dwdr dwdr[7:0] page 96 0x2d reserved ? 0x2c reserved ? 0x2b reserved ? 0x2a reserved ? 0x29 ocr0b timer/counter ? output compare register b page 72 0x28 gtccr tsm ? ? ? ? ? ? psr10 page 75 0x27 reserved ? 0x26 clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 25 0x25 reserved ? 0x24 reserved ? 0x23 reserved ? 0x22 reserved ? 0x21 wdtcr wdtif wdtie wdp3 wdce wde wdp2 wdp1 wdp0 page 39 0x20 reserved ? 0x1f reserved ? 0x1e eearl ? ? eeprom address register page 15 0x1d eedr eeprom data register page 15 0x1c eecr ? ? eepm1 eepm0 eerie eempe eepe eere page 16 0x1b reserved ? 0x1a reserved ? 0x19 reserved ? 0x18 portb ? ? portb5 portb4 portb3 portb2 portb1 portb0 page 52 0x17 ddrb ? ? ddb5 ddb4 ddb3 ddb 2 ddb1 ddb0 page 52 0x16 pinb ? ? pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 52 0x15 pcmsk ? ? pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 page 56 0x14 didr0 ? ? adc0d adc2d adc3d adc1d ain1d ain0d page 78, page 93 0x13 reserved ? 0x12 reserved ? 0x11 reserved ? 0x10 reserved ? 0x0f reserved ? 0x0e reserved ? 0x0d reserved ? 0x0c reserved ? 0x0b reserved ? 0x0a reserved ? 0x09 reserved ? 0x08 acsr acd acbg aco aci acie ? acis1 acis0 page 76 0x07 admux ? refs0 adlar ? ? ? mux1 mux0 page 90 0x06 adcsra aden adsc adate adif adie adps2 adps1 adps0 page 91 0x05 adch adc data register high byte page 92 0x04 adcl adc data register low byte page 92 0x03 adcsrb ?acme ? ? ? adts2 adts1 adts0 page 93 0x02 reserved ? 0x01 reserved ? 0x00 reserved ?
6 attiny13 2535gs?avr?01/07 note: 1. for compatibility with future devices, reserved bits shoul d be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specif ied bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only.
7 attiny13 2535gs?avr?01/07 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1
8 attiny13 2535gs?avr?01/07 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
9 attiny13 2535gs?avr?01/07 ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive). also halide free and fully green 3. for speed vs. v cc , see ?maximum speed vs. v cc ? on page 122. speed (mhz) (3) power supply ordering code package (1) operation range 10 1.8 - 5.5 attiny13v-10pi attiny13v-10pu (2) attiny13v-10si attiny13v-10su (2) attiny13v-10ssi attiny13v-10ssu (2) i ATTINY13V-10MU (2) 8p3 8p3 8s2 8s2 s8s1 s8s1 20m1 industrial (-40 c to 85 c) 20 2.7 - 5.5 attiny13-20pi attiny13-20pu (2) attiny13-20si attiny13-20su (2) attiny13-20ssi attiny13-20ssu (2) attiny13-20mu (2) 8p3 8p3 8s2 8s2 s8s1 s8s1 20m1 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s2 8-lead, 0.209" wide, plastic small outline package (eiaj soic) s8s1 8-lead, 0.150" wide, plastic gull-wing small outline (jedec soic) 20m1 20-pad, 4 x 4 x 0.8 mm body, lead pitch 0. 50 mm, micro lead frame package (mlf)
10 attiny13 2535gs?avr?01/07 packaging information 8p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
11 attiny13 2535gs?avr?01/07 8s2 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s 2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 4/7/06 8s2 d common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs are not included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 0 8 e 1.27 bsc 4 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d side view s i d e v i e w
12 attiny13 2535gs?avr?01/07 s8s1 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 9 51 3 1 title drawing no. r rev. s8s1 , 8 -le a d, 0.150" wide body, pl as tic g u ll wing s m a ll o u tline (jedec s oic) 7/2 8 /0 3 s8s 1 a common dimensions (unit of me asu re = mm) symbol min nom max note note s :1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing m s -012 for proper dimen s ion s , toler a nce s , d a t u m s ,e tc. e 5.7 9 6.20 e1 3 . 8 1 3 . 99 a1. 3 5 1.75 a1 0.1 0.25 d4. 8 04. 98 c 0.17 0.25 b 0. 3 1 0.51 l 0.4 1.27 e 1.27 b s c 0 o 8 o top view s ide view end view 1 n c a a1 b l e d e1 e
13 attiny13 2535gs?avr?01/07 20m1 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 9 51 3 1 title drawing no. r rev. 20m1 , 20-p a d, 4 x 4 x 0. 8 mm body, le a d pitch 0.50 mm, a 20m1 10/27/04 2.6 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) a 0.70 0.75 0. 8 0 a1 ? 0.01 0.05 a2 0.20 ref b 0.1 8 0.2 3 0. 3 0 d 4.00 b s c d2 2.45 2.60 2.75 e 4.00 b s c e2 2.45 2.60 2.75 e 0.50 b s c l 0. 3 5 0.40 0.55 side view pin 1 id pin #1 notch (0.20 r) bottom view top view note: reference jedec s t a nd a rd mo-220, fig . 1 (saw singulation) wggd-5. common dimensions (unit of me asu re = mm) symbol min nom max note d e e a2 a1 a d2 e2 0.0 8 c l 1 2 3 b 1 2 3
14 attiny13 2535gs?avr?01/07 errata the revision letter in this section refers to the revision of the attiny13 device. attiny13 rev. d ? eeprom can not be written below 1.9 volt 1. eeprom can not be written below 1.9 volt writing the eeprom at v cc below 1.9 volts might fail. problem fix/workaround do not write the eeprom when v cc is below 1.9 volts. attiny13 rev. b ? wrong values read after erase only operation ? high voltage serial prog ramming flash, eeprom, fuse and lock bits may fail ? device may lock for further programming ? debugwire communication not blocked by lock-bits ? watchdog timer interrupt disabled ? eeprom can not be written below 1.9 volt 1. wrong values read after erase only operation at supply voltages below 2.7 v, an eeprom location that is erased by the erase only operation may read as programmed (0x00). problem fix/workaround if it is necessary to read an eeprom location after eras e only, use an atomic write operation with 0xff as data in order to erase a location. in any case, the write only operation can be used as intended. thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. high voltage serial programming fl ash, eeprom, fuse and lock bits may fail writing to any of these locations and bits may in some occasions fail. problem fix/workaround after a writing has been initia ted, always observe the rdy/bsy signal. if the writing should fail, rewrite until the rdy/bsy verifies a correct writing. this will be fixed in revision d. 3. device may lock for further programming special combinations of fuse bits will lock the device for furt her programming effec- tively turning it into an otp device. the following combinations of settings/fuse bits will cause this effect: ? 128 khz internal oscillator (cksel[1 ..0] = 11), shortest start-up time (sut[1..0] = 00), debugwire enabled (dwen = 0) or reset disabled rstdisbl = 0. ? 9.6 mhz internal oscillator (cksel[1 ..0] = 10), shortest start-up time (sut[1..0] = 00), debugwire enabled (dwen = 0) or reset disabled rstdisbl = 0. ? 4.8 mhz internal oscillator (cksel[1 ..0] = 01), shortest start-up time (sut[1..0] = 00), debugwire enabled (dwen = 0) or reset disabled rstdisbl = 0. problem fix/ workaround avoid the above fuse combin ations. selecting longer st art-up time will eliminate the problem.
15 attiny13 2535gs?avr?01/07 4. debugwire communication not blocked by lock-bits when debugwire on-chip debug is enabled (dwen = 0), the contents of program memory and eeprom data memory can be read even if the lock-bits are set to block further reading of the device. problem fix/ workaround do not ship products with on-chip debug of the tiny13 enabled. 5. watchdog timer interrupt disabled if the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. this is only applicable in interrupt only mode. if the watchdog is configured to reset the device in the watchdog time-out following an interrupt, the device works correctly. problem fix / workaround make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. this is done by selecting a long enough time-out period. 6. eeprom can not be written below 1.9 volt writing the eeprom at v cc below 1.9 volts might fail. problem fix/workaround do not write the eeprom when v cc is below 1.9 volts. attiny13 rev. a revision a has not been sampled.
16 attiny13 2535gs?avr?01/07 datasheet revision history please note that the referring page numbers in this section are referring to this docu- ment. the referring revision in this section are referring to the document revision. changes from rev. 2535f-04/06 to rev. 2535g-01/07 changes from rev. 2535e-10/04 to rev. 2535f-04/06 changes from rev. 2535c-02/04 to rev. 2535d-04/04 changes from rev. 2535b-01/04 to rev. 2535c-02/04 changes from rev. 2535a-06/03 to rev. 2535b-01/04 1. removed preliminary. 2. updated table 12 on page 31, table 16 on page 39,table 51 on page 111. 3. removed note from table 15 on page 35. 4. updated ?bit 6 ? acbg: analog comparator bandgap select? on page 78. 5. updated ?prescaling and conversion timing? on page 83. 6. updated figure 56 on page 111. 7. updated ?dc characteristics? on page 120. 8. updated ?ordering information? on page 163. 9. updated ?packaging information? on page 164. 1. revision not published. 1. maximum speed grades changed - 12mhz to 10mhz - 24mhz to 20mhz 2. updated ?serial programming instruction set? on page 109. 3. updated ?maximum speed vs. v cc ? on page 122 4. updated ?ordering information? on page 9 1. c-code examples updated to use legal iar syntax. 2. replaced occurrences of wdif with wdtif and wdie with wdtie. 3. updated ?stack pointer? on page 9. 4. updated ?calibrated internal rc oscillator? on page 23. 5. updated ?oscillator calibration register ? osccal? on page 23. 6. updated typo in introduction on ?watchdog timer? on page 36. 7. updated ?adc conversion time? on page 84. 8. updated ?serial downloading? on page 106. 9. updated ?electrical characteristics? on page 119. 10. updated ?ordering information? on page 9. 11. removed rev. c from ?errata? on page 14. 1. updated figure 2 on page 3. 2. updated table 12 on page 31, table 17 on page 40, table 37 on page 91 and table 57 on page 121. 3. updated ?calibrated internal rc oscillator? on page 23. 4. updated the whole ?watchdog timer? on page 36. 5. updated figure 54 on page 106 and figure 57 on page 111.
17 attiny13 2535gs?avr?01/07 6. updated registers ?mcu control register ? mcucr? on page 50, ?timer/counter control register b ? tccr0b? on page 71 and ?digital input disable register 0 ? didr0? on page 78. 7. updated absolute maximum ratings and dc characteristics in ?electrical characteristics? on page 119. 8. added ?maximum speed vs. v cc ? on page 122 9. updated ?adc characteristics? on page 123. 10. updated ?typical characteristics? on page 124. 11. updated ?ordering information? on page 9. 12. updated ?packaging information? on page 10. 13. updated ?errata? on page 14. 14. changed instances of eear to eearl.
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